And it doesn’t matter.
One of the improvements Intel’s Santa Rosa platform has over the older Napa and the Napa refresh is the addition of 800MHz Front Side Bus support. However, the mobile 965 chipset (Crestline) does not support anything faster than DDR2-667 memory. Here’s the important part of the block diagram, courtesy of Intel.
As you can see, although the 800MHz FSB was added, the fastest memory supported is still 667MHz. Due to this difference, there has been quite a bit of misinformation floating around stating there would be a drastic performance difference between DDR2-667 and the unsupported DDR2-800. Many people have complained that Intel was dumb not to support DDR2-800, so that the memory could be run at the same speed as the FSB. I’m here to say that it makes very little difference.
The 800MHz FSB provides 6.4GB/s of bandwidth between the northbridge and the CPU itself. The dual channel DDR2-667 memory controller provides a theoretical 10.67GB/s of memory bandwidth, which is, for almost all all intents and purposes, enough to saturate the CPU’s processing capability. Take a look at the AnandTech memory tests on the 965 Broadwater Core 2 platform (desktop version of Crestline) and you’ll see that even with the faster 1066MHz FSB, the difference between DDR2-667 and DDR2-800 is relatively minimal, in the range of 1% to 4%. These aren’t the AthlonXP days when running the memory and FSB out of sync resulted in a drastic performance loss.
Part of the reason the Core 2 Duo doesn’t scale performance very well with faster memory is due to Intel’s very efficient memory architecture featured with the Core architecture. In fact, it comes very close to, and in some cases is more efficient than AMD K8′s integrated memory controller. Intel names these memory optimizations as part of its ‘Smart Memory Access’ technology. Here’s what Intel has to say:
Intel Smart Memory Access includes an important new capability called “memory disambiguation,” which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed.
Essentially, what Intel is saying is that Core ‘intelligently guesses’ what data it will require and loads it before all the remaining processes are completed, reducing the memory access latency.
So, the moral of the story? Intel’s Santa Rosa platform, despite supporting a 800MHz FSB doesn’t support anything faster than DDR2-667 and it doesn’t matter, because the Core architecture does a good job squeezing (nearly) all the performance it needs out of it.